#ifndef _HCIT_PARTHUS_CHIMERA_16550_SERIAL_H
#define _HCIT_PARTHUS_CHIMERA_16550_SERIAL_H

/******************************************************************************
 * MODULE NAME:    hcit_chimera_16550_serial.h
 * PROJECT CODE:   Bluestream
 * DESCRIPTION:    HCI RS232 Transport header for 16550 compatible UART on Chimera
 * AUTHOR:         John Sheehy
 * DATE:           09 March 2001
 *
 * SOURCE CONTROL: $Id: hcit_chimera_16550_serial.h,v 1.19 2009/12/23 11:39:43 tianwq Exp $
 *
 * LICENSE:
 *     This source code is copyright (c) 2001-2004 Ceva Inc.
 *     All rights reserved.
 *
 * REVISION HISTORY:
 *    09 March 2001 - Rewritten for new framework
 *
 ******************************************************************************/

#include "sys_config.h"
#include "sys_types.h"
#include "sys_features.h"
#include "sys_rda_arm.h"
/*
 * Base addresses for the two UARTs
 */
#define XR7_HCIT_UART_BASE  RDA_AHB_UART_BASE

/*
 * Offsets of registers
 */

#define XR7_HCIT_RBRTHR         0x00
#define XR7_HCIT_IER            0x04
#define XR7_HCIT_IIR            0x08
#define XR7_HCIT_FCR            0x08
#define XR7_HCIT_LCR            0x0C
#define XR7_HCIT_MCR            0x10
#define XR7_HCIT_LSR            0x14
#define XR7_HCIT_MSR            0x18

#define XR7_HCIT_COV1           0x2c
#define XR7_HCIT_COV2           0x30
#define XR7_HCIT_COV3           0x54
#define XR7_HCIT_COV4           0x58
#define XR7_HCIT_COV5           0x5c
#define XR7_HCIT_COV6           0x60
#define XR7_HCIT_COV7           0x64
#define XR7_HCIT_COV8           0x68
#define XR7_HCIT_BCSP           0x34
#define XR7_HCIT_CRC            0x38

/* FIFO trigger register */
#define XR7_HCIT_FRR                    0x24
#define XR7_FRR_TX_EMPTY_TRIGGER_BIT    9

#define XR7_HCIT_DLL            0x00

#define XR7_HCIT_DLH            0x04 /* Divisor latch high register */
#define XR7_HCIT_DL2            0x28 /* Baud Rate adjust register */
#define XR7_DEC_CNT             0x4c

/*
 * NCO is common to all three UARTs MSB of divisor latch is common, LSB is individual to each UART
 */

#define XR7_COMMON_DLM          0x04
#define XR7_COMMON_LCR          0x0C

/*
 * Interrupt Enable Bits
 */

#define XR7_IER_ERBFI           0x01
#define XR7_IER_ETBEI           0x02
#define XR7_IER_ELSI            0x04
#define XR7_IER_EDSSI           0x08
#define XR7_IER_ETOUT           0x10
#define XR7_IER_PTIME           0x80

/*
 * Interrupt ID bits
 */

#define XR7_IIR_INT_NOT_PENDING 0x01
#define XR7_IIR_MODEM           0x00
#define XR7_IIR_THRE            0x02
#define XR7_IIR_RECVBUF         0x04
#define XR7_IIR_RLS             0x06
#define XR7_IIR_TIMEOUT         0x0c
#define XR7_IIR_ID_MASK         0x0F

/*
 * Modem Control MCR
 */
#define XR7_MCR_PLSEL               0x100    /* 1:48M   0:24M */
#define XR7_MCR_AUTODETECTBAUDRATE  0x80
#define XR7_MCR_MTK_CONV_EN         0x04
#define XR7_MCR_SIRE                0x40
#define XR7_MCR_AFCE                0x20
#define XR7_MCR_LOOP                0x10
#define XR7_MCR_OUT2                0x08
#define XR7_MCR_OUT1                0x04
#define XR7_MCR_RTS                 0x02
#define XR7_MCR_DTR                 0x01

/*
 * Line status LSR
 */

#define XR7_LSR_TEMT                0x40
#define XR7_LSR_THRE                0x20
#define XR7_LSR_BI                  0x10
#define XR7_LSR_FE                  0x08
#define XR7_LSR_PE                  0x04
#define XR7_LSR_OE                  0x02
#define XR7_LSR_DR                  0x01

#define XR7_LSR_intDR               0x100

/*
 * Modem status MSR
 */

#define XR7_MSR_DCD                 0x80
#define XR7_MSR_RI                  0x40
#define XR7_MSR_DSR                 0x20
#define XR7_MSR_CTS                 0x10
#define XR7_MSR_DDCD                0x08
#define XR7_MSR_TERI                0x04
#define XR7_MSR_DDSR                0x02
#define XR7_MSR_DCTS                0x01


/*
 * FIFO Control Register FCR
 * If UART2 or UART3 are used, then
 * the FIFO levels are 1,2,3 and 4
 * as there is only a 4 byte FIFO on
 * these UARTs
 */

#define XR7_FCR_ENABLE              0x1
#define XR7_FCR_RX_FIFO_RESET       0x2
#define XR7_FCR_TX_FIFO_RESET       0x4

#define XR7_FCR_RECV_TRIGL_14       0x40
#define XR7_FCR_RECV_TRIGM_14       0x80

#define XR7_FCR_RECV_TRIGL_8        0x40
#define XR7_FCR_RECV_TRIGM_8        0x00

#define XR7_FCR_RECV_TRIGL_4        0x00
#define XR7_FCR_RECV_TRIGM_4        0x80

#define XR7_FCR_RECV_TRIGL_1        0x00
#define XR7_FCR_RECV_TRIGM_1        0x00

#define XR7_FRR_RECV_TRIG_0         0
#define XR7_FRR_RECV_TRIG_1         1
#define XR7_FRR_RECV_TRIG_2         2
#define XR7_FRR_RECV_TRIG_3         3
#define XR7_FRR_RECV_TRIG_4         4
#define XR7_FRR_RECV_TRIG_8         8
#define XR7_FRR_RECV_TRIG_14        14
#define XR7_FRR_RECV_TRIG_16        16
#define XR7_FRR_RECV_TRIG_32        32
#define XR7_FRR_RECV_TRIG_100       100
#define XR7_FRR_RECV_TRIG_254       254
#define XR7_FRR_RECV_TRIG_255       255

#define XR7_FRR_RECV_TRIG_400       400 /* used for test if overflow in register */
#define XR7_FRR_RECV_TRIG_480       480

#define XR7_COV1_CHANGE_BYTE1_2     0xff0000
#define XR7_COV1_CHANGE_BYTE1_1     0x00ff00
#define XR7_COV1_SEARCH_BYTE        0x0000ff

#define XR7_COV2_CHANGE_BYTE2_2     0xff0000
#define XR7_COV2_CHANGE_BYTE2_1     0x00ff00
#define XR7_COV2_SEARCH_BYTE        0x0000ff

#define XR7_BCSP_CRC_RESET_RX       0x20
#define XR7_BCSP_CRC_ENABLE_RX      0x10
#define XR7_BCSP_CONVERT_ENABLE_RX  0x08
#define XR7_BCSP_CRC_RESET_TX       0x04
#define XR7_BCSP_CRC_ENABLE_TX      0x02
#define XR7_BCSP_CONVERT_ENABLE_TX  0x01

#define XR7_CRC_RESULT_RX_MASK      0xffff0000
#define XR7_CRC_RESULT_TX_MASK      0x0000ffff

/*
 * UART register access macro
 * The first pair get/set registers from the chosen UART, the latter
 * access the "common UART" registers (which are located at UART1 )
 *
 * NOTE: The u_int16* is required as only 16 and 32 bit register accesses
 * will activate the correct signals needed to access the UART on the XR7. The unused
 * 8 bits are thrown away.
 */

#define mHCIT_CHIMERA_GET_REG(x)            (*(volatile u_int32*)(XR7_HCIT_UART_BASE + (x)))
#define mHCIT_CHIMERA_SET_REG(r,x)          (*(volatile u_int32*)(XR7_HCIT_UART_BASE + (r))) = (u_int32)(x)

#define mHCIT_CHIMERA_GETBYTE_REG(x)        (*(volatile u_int8*)(XR7_HCIT_UART_BASE + (x)))
#define mHCIT_CHIMERA_SETBYTE_REG(r,x)      (*(volatile u_int8*)(XR7_HCIT_UART_BASE + (r))) = (u_int8)(x)

#define mHCIT_CHIMERA_GET_REG_COMMON(x)     (*(volatile u_int32*)(XR7_HCIT_UART_BASE + (x)))
#define mHCIT_CHIMERA_SET_REG_COMMON(r,x)   (*(volatile u_int32*)(XR7_HCIT_UART_BASE + (r))) = (u_int32)(x)

/*
 * Function Interfaces
 */

void HCIT_Chimera_16550_Initialise(u_int32 baud_rate, u_int32 uart_setting);
void HCIT_Chimera_16550_Shutdown(void);
void HCIT_Chimera_16550_Restart(void);


void HCIT_Chimera_16550_Tx_Block(volatile u_int8 **bufp, volatile u_int32 *length, u_int8 flag, void (*txcb)(void));
void HCIT_Chimera_16550_Tx_Char_Polled(volatile u_int8 **bufp, volatile u_int32 *length, u_int8 flag);

u_int16 HCIT_Chimera_16550_Get_Char(void);
void HCIT_Chimera_16550_Setup(volatile u_int8 *rx_buffer, u_int16 rx_length, u_int8 flag);

void HCIT_Chimera_16550_Interrupt_Handler(void);
void HCIT_Chimera_16550_Empty_FIFO(void);

void HCIT_Chimera_16550_Set_AutoBaudRate_Enable(boolean enable);
void  HCIT_Chimera_16550_Set_BaudRate(u_int32 baud_rate);

void HCIT_Chimera_16550_Empty_TXFinish(void);
#endif /* _PARTHUS_HCIT_CHIMERA_SERIAL_H */
